Adding electronics

This commit is contained in:
Elena Arenskötter 2023-11-04 13:51:50 +01:00
parent a6a0fedfeb
commit 710a0327a7
25 changed files with 47930 additions and 0 deletions

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[submodule "electronics/InterferometerControl/teensy.pretty"]
path = electronics/InterferometerControl/teensy.pretty
url = https://github.com/XenGi/teensy.pretty

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datasheets/AD694.pdf Normal file

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datasheets/Si2304.pdf Normal file

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datasheets/lm4871.pdf Normal file

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EESchema-DOCLIB Version 2.0
#
#End Doc Library

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Cmp-Mod V01 Created by PcbNew date = Mon 04 Sep 2017 07:48:59 AM CDT
BeginCmp
TimeStamp = 580CBA7A
Path = /5834FB2E
Reference = MK1;
ValeurCmp = M2.5;
IdModule = Mounting_Holes:MountingHole_2-5mm;
EndCmp
BeginCmp
TimeStamp = 580CBAAE
Path = /5834FC19
Reference = MK2;
ValeurCmp = M2.5;
IdModule = Mounting_Holes:MountingHole_2-5mm;
EndCmp
BeginCmp
TimeStamp = 580CBAC8
Path = /5834FBEF
Reference = MK3;
ValeurCmp = M2.5;
IdModule = Mounting_Holes:MountingHole_2-5mm;
EndCmp
BeginCmp
TimeStamp = 580C7F66
Path = /580C18BB
Reference = P1;
ValeurCmp = CONN_02X20;
IdModule = Socket_Strips:Socket_Strip_Straight_2x20;
EndCmp
BeginCmp
TimeStamp = 580CBAD7
Path = /5834FC4F
Reference = MK4;
ValeurCmp = M2.5;
IdModule = Mounting_Holes:MountingHole_2-5mm;
EndCmp
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update=07.07.2022 11:11:45
version=1
last_client=kicad
[cvpcb]
version=1
NetITyp=0
NetIExt=.net
PkgIExt=.pkg
NetDir=
LibDir=
NetType=0
[cvpcb/libraries]
EquName1=devcms
[general]
version=1
[eeschema]
version=1
LibDir=
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=InterferometerControl.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1524
MinViaDiameter=0.7999999999999999
MinViaDrill=0.5
MinMicroViaDiameter=0.5
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.2
ViaDiameter1=0.9
ViaDrill1=0.6
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.09999999999999999
CopperTextSizeV=1
CopperTextSizeH=1
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.09999999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.12
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=0
[pcbnew/Layer.B.CrtYd]
Enabled=0
[pcbnew/Layer.F.CrtYd]
Enabled=0
[pcbnew/Layer.B.Fab]
Enabled=0
[pcbnew/Layer.F.Fab]
Enabled=0
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.2
ViaDiameter=0.9
ViaDrill=0.6
uViaDiameter=0.5
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Power
Clearance=0.2
TrackWidth=0.5
ViaDiameter=1
ViaDrill=0.7
uViaDiameter=0.5
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

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(rules PCB InterferometerControl
(snap_angle
fortyfive_degree
)
(autoroute_settings
(fanout off)
(autoroute on)
(postroute on)
(vias on)
(via_costs 50)
(plane_via_costs 5)
(start_ripup_costs 100)
(start_pass_no 1601)
(layer_rule F.Cu
(active on)
(preferred_direction horizontal)
(preferred_direction_trace_costs 1.0)
(against_preferred_direction_trace_costs 2.2)
)
(layer_rule B.Cu
(active on)
(preferred_direction vertical)
(preferred_direction_trace_costs 1.0)
(against_preferred_direction_trace_costs 1.9)
)
)
(rule
(width 200.0)
(clear 200.2)
(clear 100.0 (type smd_to_turn_gap))
(clear 50.0 (type smd_smd))
)
(padstack "Via[0-1]_900:600_um"
(shape
(circle F.Cu 900.0 0.0 0.0)
)
(shape
(circle B.Cu 900.0 0.0 0.0)
)
(attach off)
)
(padstack "Via[0-1]_1000:700_um"
(shape
(circle F.Cu 1000.0 0.0 0.0)
)
(shape
(circle B.Cu 1000.0 0.0 0.0)
)
(attach off)
)
(via
"Via[0-1]_900:600_um" "Via[0-1]_900:600_um" default
)
(via
"Via[0-1]_1000:700_um" "Via[0-1]_1000:700_um" default
)
(via
"Via[0-1]_900:600_um-kicad_default" "Via[0-1]_900:600_um" "kicad_default"
)
(via
"Via[0-1]_1000:700_um-kicad_default" "Via[0-1]_1000:700_um" "kicad_default"
)
(via
"Via[0-1]_900:600_um-Power" "Via[0-1]_900:600_um" Power
)
(via
"Via[0-1]_1000:700_um-Power" "Via[0-1]_1000:700_um" Power
)
(via_rule
default "Via[0-1]_900:600_um"
)
(via_rule
"kicad_default" "Via[0-1]_900:600_um-kicad_default"
)
(via_rule
Power "Via[0-1]_1000:700_um-Power"
)
(class default
(clearance_class default)
(via_rule default)
(rule
(width 200.0)
)
(circuit
(use_layer F.Cu B.Cu)
)
)
(class "kicad_default"
+3V3 +5V GND "/ID_SD" "/ID_SC" /GPIO5 /GPIO6 /GPIO26
"/GPIO2(SDA1)" "/GPIO3(SCL1)" "/GPIO4(GCLK)" "/GPIO14(TXD0)" "/GPIO15(RXD0)" "/GPIO17(GEN0)" "/GPIO27(GEN2)" "/GPIO22(GEN3)"
"/GPIO23(GEN4)" "/GPIO24(GEN5)" "/GPIO25(GEN6)" "/GPIO18(GEN1)(PWM0)" "/GPIO10(SPI0_MOSI)" "/GPIO9(SPI0_MISO)" "/GPIO11(SPI0_SCK)" "/GPIO8(SPI0_CE_N)"
"/GPIO7(SPI1_CE_N)" "/GPIO12(PWM0)" "/GPIO13(PWM1)" "/GPIO19(SPI1_MISO)" /GPIO16 "/GPIO20(SPI1_MOSI)" "/GPIO21(SPI1_SCK)" "Net-(C1-Pad1)"
"Net-(C1-Pad2)" "Net-(Q1-Pad1)" "Net-(Q1-Pad2)" "Net-(CON5-Pad2)" "Net-(CON1-Pad1)" "Net-(R1-Pad1)" "Net-(CON2-Pad1)" "Net-(R4-Pad1)"
"Net-(R7-Pad1)" "Net-(CON6-Pad1)" "Net-(U1-Pad17)" "Net-(U1-Pad18)" "Net-(U1-Pad19)" "Net-(U1-Pad15)" "Net-(U1-Pad14)" "/TEENSY_A0"
"/TEENY_A1" "/TEENY_A2" "/TEENY_A3" "Net-(U1-Pad25)" "Net-(U1-Pad26)" "Net-(U1-Pad27)" "Net-(U1-Pad28)" "Net-(U1-Pad29)"
"Net-(U1-Pad30)" "Net-(U1-Pad31)" "Net-(U1-Pad33)" "Net-(U1-Pad11)" "Net-(U1-Pad10)" "Net-(U1-Pad4)" "Net-(U1-Pad3)" "Net-(U1-Pad2)"
"Net-(U1-Pad1)" "Net-(U1-Pad35)" "Net-(U1-Pad36)" "Net-(U1-Pad37)" "Net-(U1-Pad38)" "Net-(U1-Pad39)" "Net-(U1-Pad40)" "Net-(U1-Pad41)"
"Net-(U1-Pad42)" "Net-(U1-Pad43)" "Net-(U1-Pad44)" "Net-(CON3-Pad1)" "Net-(U4-Pad8)" "Net-(U5-Pad5)" "Net-(U5-Pad6)" "Net-(J1-Pad1)"
"Net-(C10-Pad1)" /Vref "Net-(C11-Pad1)" "Net-(C12-Pad1)" "Net-(C12-Pad2)" "Net-(C13-Pad2)" "Net-(CON1-Pad2)" "Net-(J3-Pad1)"
/ch0 /ch1 /DAC2 "Net-(U8-Pad6)" "Net-(U8-Pad7)" "Net-(U8-Pad8)" "Net-(U8-Pad19)"
(clearance_class "kicad_default")
(via_rule kicad_default)
(rule
(width 200.0)
)
(circuit
(use_layer F.Cu B.Cu)
)
)
(class Power
(clearance_class Power)
(via_rule Power)
(rule
(width 500.0)
)
(circuit
(use_layer F.Cu B.Cu)
)
)
)

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comp = "P1" module = "HE10_26D"

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(fp_lib_table
(lib (name teensy)(type KiCad)(uri ${KIPRJMOD}/teensy.pretty)(options "")(descr ""))
)

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(sym_lib_table
(lib (name InterferometerControl-rescue)(type Legacy)(uri ${KIPRJMOD}/InterferometerControl-rescue.lib)(options "")(descr ""))
(lib (name teensy)(type Legacy)(uri ${KIPRJMOD}/teensy_library/teensy.lib)(options "")(descr ""))
)

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Subproject commit ab50abcedbe69716f4f3d0925abb24e38a32a332

@ -0,0 +1 @@
Subproject commit 6f0ed76aa1e392bf9a35a5e5e51ecb9f598c4f37

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electronics/sboa327a.pdf Normal file

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electronics/slau502.pdf Normal file

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